1. Field of the Invention
The present invention relates to a layout design program, a layout design device and a layout design method for a semiconductor integrated circuit. More particularly, a layout design program, a layout design device and a layout design method for a semiconductor integrated circuit including a plurality of circuit blocks.
2. Description of the Related Art
As is called an age of system-on-silicone (system-on-chip) wherein all the systems have been installed in one semiconductor integrated circuit (one chip) in recent years, semiconductor integrated circuits have been getting larger in its integration density. There is a demand to realize a highly integrated LSI operating at a high frequency, which is increasing a difficulty in terms of a design. In the process of designing a large-scale semiconductor integrated circuit, a critical factor is to obtain an optimal floorplanning in a floorplanning stage before processing placement and routing in order to realize an operation at a high operational frequency and a highly integrated layout.
In the layout of a semiconductor integrated circuit including a plurality of circuit blocks, a floorplanning design is carried out in a manner such that routing congestion is taken into account in the floorplanning stage on the basis of the number of interconnections among circuit blocks. In the above floorplanning design, it is impossible to take into account a timing constraints among the circuit blocks during designing the floorplanning. As a result, a timing violation is found out after implementing the placement and routing, causing numerous repetitions of returning to the floorplanning design. Hence, an enormous design TAT (Turn Around Time) is required.
A conventional floorplanning design tool has a function to take into account the routing congestion on the basis of the number of the interconnections among the circuit blocks in designing the floorplanning for a plurality of the circuit blocks in order to realize a floorplanning with little routing congestion problem. However, the floorplanning design function is not perfectly realized yet in designing the floorplanning for a plurality of the circuit blocks in terms of confirming the timing constraints among the circuit blocks and doing placement of the circuit blocks in a position to prevent the violations of the timing constraints. The conventional floorplanning design tool has a supplemental technique described below to do placement the circuit blocks without having the violations of the timing constraints.
Japanese Laid-Open Patent Application JP-P2002-366598A discloses a technique to enable the reduction of the floorplanning preparation time by prioritizing circuit blocks to be placed close to each other. This floorplanning preparation method for the semiconductor chip includes a process of performing static timing analysis and a process of prioritizing the circuit blocks to be placed close to each other. In the process of performing the static timing analysis, the static timing analysis is carried out by setting ranges in delay values among the circuit blocks calculated based on a tentative interconnect capacitance. In the process of prioritizing the circuit blocks to be placed close to each other, these circuit blocks are prioritized by using results of the static timing analysis. Moreover, in the process of prioritizing the circuit blocks to be placed close to each other, these circuit blocks may be prioritized based on the results of the static timing analysis and the portion of the number of the interconnections among the circuit blocks. Further, in the process of prioritizing the circuit blocks to be placed close to each other, these circuit blocks may be prioritized based on the weighted values for the results of the static timing analysis and the portion of the number of the interconnections among the circuit blocks. Furthermore, in the process of prioritizing the circuit blocks to be placed close to each other, these circuit blocks may be prioritized based on both the weighted values for the results of the static timing analysis and the portion of the number of the interconnections among the circuit blocks.
FIG. 1 is the flowchart showing a floorplanning preparation method in the semiconductor chip. In a step S81, delay values among the circuit blocks under the worst condition of a manufacturing process, temperature and voltage are calculated based on the tentative interconnect capacitance among the circuit blocks on the basis of a netlist. In a step S82, the calculated delay value among the circuit blocks is multiplied by each of coefficients for a close distance, a remote distance and an average distance among the circuit blocks. These coefficients are prepared in advance. The delay values are thus calculated in the cases of the circuit blocks placed closely (under), remotely (over) and in the average distance (center). In a step S83, the static timing analysis is carried out on the basis of the three kinds of the delay values among the circuit blocks. Based on the result of the static timing analysis, a path violating the timing constraints among certain circuit blocks is identified. In the following step S84, the order of placing the circuit blocks, which violate the timing constraints, is calculated on the basis of a certain equation. Once the order of the placement is calculated, the priority of the circuit blocks to be placed close to each other is determined, which is outputted as floorplanning information. Then, the floorplanning design is performed based on the floorplanning information in a step S85.
As described above, this technique is intended to prioritize the order of placing the circuit blocks for reducing the floorplanning preparation time. However, the TAT of the floorplanning preparation is increased and the floorplanning may not be optimized.
(1) The above-described technique is capable of obtaining the information on the priority of the circuit blocks to be placed close to each. However, since the information does not include distances among the circuit blocks which are concrete data to make a decision how far these circuit blocks are placed away from each other when these circuit blocks are actually placed on the chip in the floorplanning design, it is impossible to obtain an allowable range among the circuit blocks. Therefore, when there are a number of circuit blocks to be placed on the chip, even if the circuit blocks are placed in accordance with the priority order of the circuit blocks to be placed close to each, it may be required to set a great distance among the circuit blocks due to the large number of the circuit blocks. In this case, there is no information on the range of the distance among the circuit blocks in which the timing constraints is satisfied. As a result, the floorplanning is prepared without satisfying the timing constraints and the TAT of the floorplanning preparation may be increased.
(2) In an actual layout, an interconnect detour due to a routing congestion causes deterioration of routing convergence (routing closure). In the above-described technique, preparation of information is limited to the circuit blocks to be placed close to each other. As a result, the routing congestion is not considered and optimization of the floorplanning in consideration with the routing congestion may not be realized.
Japanese Laid-Open Patent Application JP-P2003-330986A also discloses a design method of the semiconductor integrated circuit to solve problems of a placement and routing congestion or a violation of a timing constraints without increasing the chip area and causing retrogressive operations such as repetitive floorplanning or RTL corrections. This design method of the semiconductor integrated circuit is a design method to design a layout of the semiconductor integrated circuit including a plurality of blocks configured with a functional micro such as a logic cell and a memory, and having interconnections to connect these blocks. The design method for a layout design includes a step of confirming the state of congestion, a step of confirming a violation of timing constraints and a step of changing the shape of the blocks. In the step of confirming the state of congestion, the states of the placement congestion and the routing congestion inside/outside the blocks are confirmed. In the step of confirming the violation of the timing constraints, the violations of the timing constraints inside/outside the blocks are confirmed. In the step of changing the shape of the blocks, the shapes of the blocks are changed in accordance with the congestion states of the placement and the routing and the violation of the timing constraints. The design method for the layout design further has steps of re-placement and re-routing to mitigate the violation of the timing constraints. In the step of the re-placement and re-routing, the re-placement and re-routing are implemented to mitigate the violation of the timing constraints with respect to the placement change of the logic cell and the functional micro inside the blocks and the routing change inside/outside the blocks that are caused by the change of the shapes of the blocks. The design method for the layout design also has steps of re-placement and re-routing to mitigate the placement and routing congestion. In these steps of the re-placement and re-routing, the re-placement and re-routing are implemented to mitigate the placement and routing congestion with respect to the placement change of the logic cell and the functional cell inside the blocks caused by the change of the shape of the blocks.
FIG. 2 is a flowchart showing the above-described design method of the semiconductor integrated circuit. First of all, the placement and routing result, the timing constraints and library are supplied (step S91). Then, the step of changing the shape of the blocks is carried out (step S93). Finally, the result is outputted (step S98). The change of the shape of the blocks in the step S93 is carried out in the following procedures.
The state of the placement and the routing congestion inside/outside the blocks, and the violation of the timing constraints are confirmed first (step S94). Then, the shape of the blocks are determined in order to solve the problem of the routing congestion and violation of the timing constraints which were confirmed in the foregoing step (step S95). Specifically, the block shapes are determined for change in the following three principles. First one is to change the block shape for expanding the area in which the interconnections are congested. Second one is to expand the shape of the block in which the violation of a set-up timing constraints is observed so that the distance among the blocks are shortened. Third one is to reduce the shape of the blocks in which the violation of a hold timing constraints is observed so that the distance among the blocks are expanded. The changes of the block shapes are thus determined (step S96). Thereafter, the placement and the routing are changed with respect to the area in which the shape of the block was changed (step S97).
The block shapes are thus changed, and the output result of the placement and routing in which the placement and the routing have been changed is provided in the step S98. In this technique, however, cases are expected as follows wherein the routing congestion and the violation of the timing constraints are not corrected, and causing another routing congestion and another violation of the timing constraints.
(1) This technique is intended to solve the placement and routing congestion and the violation of the timing constraints by changing the block shapes based on the result of the placement and routing. However, the floorplanning design must be implemented before obtaining the result of the placement and routing in practice. In this stage of the floorplanning, the result of the placement and routing does not exist. Therefore, the above method can not be applied to prepare a floorplanning in consideration with the placement and routing congestion and the timing constraints. Therefore, without optimizing the floorplanning subjected to the placement and routing, there will be a case in which the change of the block shapes on the basis of the placement and routing result does not make a correction of the routing congestion and violation of the timing constraints.
(2) When a portion having the routing congestion and a portion having the violation of the timing constraints are concentrated or overlapped, the above technique is intended to solve these problems by changing the shape of the relevant blocks. In other words, since the only blocks having these problems are exclusively considered, another routing congestion or another violation of the timing constraints among another surrounding blocks or in another surrounding areas may occur after this technique is carried out.
(3) Moreover, when the violation of the set-up timing constraints and the violation of the hold timing constraints are observed at the same time, the floorplanning may not be achieved convergence by simply expanding or reducing the block shape. The change of the block shape for correcting the set-up timing violation reduces the distance among the blocks, which may cause the hold timing violation. On the contrary, the change of the block shape for correcting the hold timing violation expands the distance among the blocks, which may cause the set-up timing violation. Therefore, it may be impossible to prepare a floorplanning to achieve the simultaneous convergence of the violations in both the set-up timing constraints and the hold timing constraints.
As described above, these techniques can not take into account both the routing congestion and the timing constraints at the same time in designing the floorplanning of the semiconductor devices. Consequently, the convergence of both the routing congestion and the violation of the timing constraints may not be achieved, which will result in repetitive processing from the floorplanning design to the placement and routing design.
As described above, the conventional floorplanning process employs a method for placing the circuit blocks on a chip and determining the shape of the circuit blocks on the basis of the connection relation strength among the circuit blocks. Accordingly, the routing congestion among the circuit blocks can be considered on the basis of the connecting relation strength among the circuit blocks. However, it is not known until practically implementing the placement and routing to find out whether the placement of the circuit blocks was determined to satisfy a timing constraints to be demanded in the final stage. Therefore, in order to obtain a floorplanning without having a routing congestion and satisfying timing constraints, repetitive processes from designing the floorplanning to the designing of routing are required. As a result, an enormous design TAT is necessary.